Integrated circuits (ICs) include many transistors formed on a single semiconductor substrate. As IC technology has progressed, the density of transistors formed on a single semiconductor substrate has increased rapidly. Currently, ICs such as ultra-large scale integrated (ULSI) circuits can include more than a million transistors. To allow continued increase in both the number of transistors and the density of transistors on an integrated circuit, new methods of fabricating ICs must be developed.
Traditional fabrication methods utilize conventional optical lithography techniques to define transistors over a semiconductor substrate. Conventional optical lithography includes the following steps: (1) forming a photoresist material over a nitride layer, (2) exposing areas of the photoresist to radiation through a mask containing a transistor pattern, (3) developing the photoresist such that it becomes soluble to a specific solvent at locations where the transistors are to be located, (4) removing the developed photoresist to expose the transistor areas on the nitride layer, and (5) removing the nitride layer at locations exposed through the photoresist layer. After optical lithography, active regions for transistors can be provided through voids in the nitride layer formed by lithography.
While providing a valuable method of defining transistor areas over a semiconductor substrate, conventional optical lithography has various limitations. For example, during the exposure step, areas outside of the transistor areas are unintentionally exposed to reflected radiation. This uncontrolled exposure to reflected radiation limits transistor pattern precision and, ultimately, transistor density. FIG. 1, a cross-sectional view of pattern imprecision resulting from reflected radiation, shows a portion 1 of an integrated circuit including a nitride layer 2 and an underlying layer 3. Portion 1 illustrates various problems resulting from conventional optical lithography. Specifically, four undesirable characteristics of apertures in the nitride layer are illustrated: (1) a footed aperture 4, (2) an undercut aperture 5, (3) a re-entrant aperture 6, and (4) a tapered aperture 7. The unpredictable and undesirable aperture characteristics shown in portion 1 limit transistor density. Although the problems shown on portion 1 in FIG. 1 are shown on one substrate, only one or two types of problems are typically present on any one substrate.
The imprecision of conventional optical lithography represents a barrier to continuous scaling of MOS transistors to a 0.05 um generation and below. Where IC fabrication requires patterning of gate lines with very small dimensions (e.g., 10-30 nm), use of conventional optical lithography will be very difficult or even impossible.
Thus, there is a need for a non-lithographic or "maskless" process for fabricating small dimension transistors. Further still, there is a need to minimize gate sheet resistance in the transistors formed using the maskless process. Gate sheet resistance should be minimized as RC delay is considered one of the most important factors that impact circuit performance. (e.g., circuit speed).